Non-conductive circuit boards printed with conductive traces, commonly referred to as Printed Circuit Boards (PCBs), are used extensively in commercial electronics. Electronic components are connected to a PCB, and the traces are formed to realize the desired connection there between. The first PCBs were one non-conductive layer with one layer for the conductive traces, or interconnect. To reduce the size of PCBs or to make it possible to realize a complicated circuit, multi-level PCBs were developed.
A multi-level PCB consists of multiple non-conductive layers interspersed with interconnect layers. A via through a layer of a PCB is used to connect a conductive trace on one interconnect layer with that of another. FIGS. 1A-1C illustrate the construction of a via on a multi-layered PCB.
In FIG. 1A is a cross-sectional view of a portion of a PCB 1 showing multiple layers of non-conductive material 2 and multiple layers of conductive traces (i.e., a trace on the top of the PCB, 5 layers of traces within the PCB, and one trace on the bottom of the PCB. In the example, the second 3 and fourth 4 embedded traces, counting from the top of the PCB, are desired to be connected by a via. Epoxy reinforced with fiberglass is typically used for the non-conductive layers 2. Copper is typically used for the conductive traces.
FIG. 1B is a cross-sectional view of the PCB of FIG. 1A, where a hole has been drilled through the PCB and through the second 3 and fourth 4 embedded traces.
FIG. 1C is a cross-sectional view of the PCB of FIG. 1B, where conductive material 6 has been plated in the formed in FIG. 1B. The plated material electrically connects the second 3 and fourth conductive traces, but does not connect to any other conductive trace.
The frequency at which electronic components can operate has steadily increased over the years. To realize the maximum operating frequency of an electronic component, resistance and dielectric losses of the interconnect layers connected to the component should be minimized. However, increased operating frequencies with their attendant shorter wavelengths increase the likelihood of generating radio frequency interference (RFI) on a PCB. FIG. 2 illustrates one possible way of generating RFI on a PCB.
FIG. 2 is a cross-sectional view of a portion of a PCB 21. The PCB 21 includes a first via 22 and a second via 23. The first via 22 electrically connects a first conductive trace 24 on the second embedded conductive layer of the PCB, counting from the top of the PCB, to a second conductive trace 25 on the fifth embedded conductive layer. The second via 23 connects the second conductive trace 25 to a third conductive trace 26 on the same embedded conductive layer as well as possibly to a surface mounted component. A first arrow 27 indicates the preferred path of a signal traversing the interconnection formed by the vias 22, 23, and the conductive traces 24, 25, 26. However, at a sufficiently high frequency, RFI may be created when the intended signal encounters a via. Two examples of this are indicated by the second arrow 28 and the third arrow 29. The second arrow 28 indicates RFI that traverses the PCB, guided by solid plane layers 26A and 26B, whereas the third arrow 29 indicates RFI that reflects off of the second via 23. The fourth arrow 29A indicates energy that can be resonantly amplified by the high Q via stubs associated with via 23. Since RFI can disrupt operation of electronic components on or off of the PCB, there is a need to reduce or eliminate such RFI.
U.S. Pat. Nos. 6,538,538 and 6,661,316, each entitled “HIGH FREQUENCY PRINTED CIRCUIT BOARD VIA,” disclose a via that includes a conductive pad surrounding the conductor and embedded within the PCB to increase the frequency at which electronics can operate. Such a via increases the likelihood of generating RFI, not reduces or eliminates RFI as does the present invention. U.S. Pat. Nos. 6,538,538 and 6,661,316 are hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,541,712 entitled “HIGH SPEED MULTI-LAYER PRINTED CIRCUIT BOARD VIA,” discloses a via for eliminating or reducing RFI caused by a via by reducing the length of the via using an insulator. The present invention does not reduce the length of a via using an insulator as does U.S. Pat. No. 6,541,712. U.S. Pat. No. 6,541,712 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,621,012, entitled “INSERTION OF ELECTRICAL COMPONENT WITHIN A VIA OF A PRINTED CIRCUIT BOARD,” discloses a method of reducing impedance of a via by inserting an electrical component into the via. Reducing impedance does not necessarily eliminate RFI as does the present invention. U.S. Pat. No. 6,621,012 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,983,535, entitled “INSERTION OF ELECTRICAL COMPONENT WITHIN A VIA OF A PRINTED CIRCUIT BOARD,” discloses a method of reducing impedance of a via by inserting an electrical component into the via. Reducing impedance does not necessarily eliminate RFI as does the present invention. U.S. Pat. No. 6,983,535 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20040212972, entitled “PRINTED CIRCUIT BOARD MINIMIZING UNDESIRABLE SIGNAL REFLECTIONS IN A VIA AND METHODS THEREOF,” discloses a method of minimizing signal reflectance by avoiding long conductive vias and using, instead, non-conductive vias and inserting conductive elements into the via to connect conductive traces on either side of the via, where the conductive element is only long enough to connect the conductive traces, but not long enough to cause signal reflections. The present invention does not employ non-conductive vias and conductive elements that are only large enough to make the desired connection. U.S. Pat. Appl. No. 20040212972 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20040238216, entitled “VIA SHIELDING FOR POWER/GROUND LAYERS ON PRINTED CIRCUIT BOARD,” discloses a method of adding an insulating material around a conductive layer to prevent short circuits with a power or ground line if a via hole is drilled improperly. U.S. Pat. Appl. No. 20040238216 does not reduce or eliminate RFI as does the present invention. U.S. Pat. Appl. No. 20040238216 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20050230813, entitled “PRINTED CIRCUIT BOARD INCLUDING VIA CONTRIBUTING TO SUPERIOR CHARACTERISTIC IMPEDANCE,” discloses a method of forming a conductive ring around a via to facilitate impedance matching and, thus, better suppress noise. The present invention does not employ a conductive ring around a via as does U.S. Pat. Appl. No. 20050230813. U.S. Pat. Appl. No. 20050230813 is hereby incorporated by reference into the specification of the present invention.